首頁 > 網路資源 > 大同大學數位論文系統

博碩士論文 etd-1014108-104304 詳細資訊


姓名 周煥庭 (Huan-Ting Zhou) 電子郵件信箱 不公開
系所 電機工程學系(所) (Electrical Engineering)
學位 碩士 (Master) 學年 / 學期 97 學年第 1 學期
論文名稱(中) 8位元50MHZ取樣頻率之CMOS管線類比數位轉換器
論文名稱(英) A 8-BIT 50-MS/s CMOS PIPELINE ANALOG TO DIGITAL CONVERTER
檔案 本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 使用者自訂:校內 2 年後公開、校外永不公開
論文種類 碩士論文
論文語文別 / 頁數 中文 / 74
統計 已被瀏覽 2618 次,被下載 10 次
關鍵字(中)
  • 類比數位轉換器
  • 管線式
  • 關鍵字(英)
  • ADC
  • Pipeline
  • 摘要(中) 在現今許多的應用當中,大多使用數位訊號處理技術來處理所傳輸的資料,因此,在接收到的類比訊號級數位訊號處理系統間,就需要將類比訊號轉換成數位訊號的介面。由於近年來無線通訊系統和個人可攜式電子產品的成長,對於低功率的電路也有著不可或缺的需求。在許多種類的CMOS類比數位轉換器的架構中,由於管線式類比數位轉換器每一級的取樣保持電路如同快閃式類比數位轉換器一樣能同時動作,因此管線式類比數位轉換能達到高速的輸入性能和快速的處理能力。在本篇論文中,針對高速度的管線式類比數位轉換器做設計,並且在設計過程中盡可能的減低消耗功率。
    在本篇論文中,使用了台積電0.18微米互補式金氧半製程設計與實現一個八位元,50MHz 取樣頻率的 CMOS 管線式類比數位轉換器,每一個階段為1.5 位元的解析度。根據模擬結果,整體電路在50 MHz 的取樣頻率下 SNR 為 48.81 dB,可達7.81位元的精確度,功率消耗為 105 mW。
    摘要(英) Many of the applications nowadays utilize the digital signal processing (DSP) to resolve the transmitted information. Therefore, an analog to digital interface is required between the received analog signal and DSP system and portable consumer electronics, the demand for low-power integrated circuits is indispensable. In many types of CMOS analog to digital converter (ADC) architectures, a pipelined architecture can archive good dynamic range performances and the same throughput as the flash ADC due to the pipelined operation in each range. This thesis focuses on the high-speed design of pipelined ADC. In the meanwhile, we try to minimize the power dissipations as well.
    In this thesis, an 8-bit 50MHz pipelined A/D converter, with 1.5-bit resolution per stage, has been successfully designed and implemented using the TSMC 0.18μm 1P6M CMOS process. Simulation results show that the designed pipelined ADC can operate at 50MHz with 48.84dB signal- to- noise ratio – conforming to the 7.81-bit accuracy, and the estimated power dissipation is about 105 mw.
    論文目次 ABSTRACT i
    中文摘要 ii
    致謝 iii
    章節目錄 iv
    圖目錄 vii
    表目錄 viii
    第一章 緒論 1
    1.1 研究動機 1
    1.2 論文結構 2
    第二章 中高速類比數位轉換器架構概論 3
    2.1 簡介 3
    2.2 理想類比數位轉換器(Ideal A/D Converter) 3
    2.3.1 動態特性 5
    2.3.2 靜態特性 9
    2.4 高速類比數位轉換器之架構介紹 12
    2.4.1快閃式類比數位轉換器(Flash analog to digital converter) 12
    2.4.2兩階段式類比數位轉換器(Two step analog to digital converter) 14
    2.4.3管線式類比數位轉換器(Pipeline analog to digital converter) 16
    2.5 數位錯誤修正原理及1.5-bit管線式類比對數位轉換器 20
    第三章 全差動運算放大器之設計 25
    3.1簡介 25
    3.2 運算放大器所需之規格 26
    3.3 單級運算放大器 31
    3.3.1伸縮式(Telescopic)運算放大器 31
    3.3.2摺疊疊接式(Folded cascode)運算放大器 32
    3.4 雙級式(Two stage)運算放大器 34
    3.4.1雙級式(Gain Boosting Operation Amplifier) 38
    第四章 管線式類比數位轉換器之分析與設計 40
    4.1 簡介 40
    4.2 開關式電容(Switched capacitor, SC)電路 40
    4.2.1 MOS開關 40
    4.2.2通道電荷注入效應(Charge injection) 43
    4.2.3 時脈饋入效應(Clock feed-through) 46
    4.3 前端取樣及保持電路(Sample and hold circuit,S/H) 47
    4.4 子類比數位轉換器(Sub-ADC) 50
    4.4.1比較器電路 50
    4.4.2 1.5-bit子類比數位轉換器(sub-ADC) 53
    4.4.3 2-bit類比數位轉換器 55
    4.5 DAC/減法器/增益級(Multiplying DAC, MDAC) 56
    4.6 時脈產生器(Clock Generator) 61
    4.7 暫存器(Register) 62
    4.8 加法器(Adder) 64
    4.9 8-bit 管線式ADC模擬結果 67
    第五章 結論與未來工作 72
    參考文獻 73
    參考文獻 [1] R. Jacob Baker,"CMOS Mixed-Signal Circuit Design," John Wiley & Sons, Boston, June. 2002.
    [2] Behzad Razavi, "Design of Analog CMOS Integrated Circuit," McGraw-Hill, Boston, 2001.
    [3] Hsiang-Wei Liu, "A 1-V 10-Bit Pipelined A/D Converter Based on Switched-Opamp Technique," Master Thesis, Nation Cheng Kung University, June. 2004.
    [4] T. Cho and P. R. Gray, "A 10 b, 20 Msamples/s, 35mW Pipeline A/D Converter," IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.
    [5] M. Gustavsson, J. J. Wilner and N. N. Tan, "CMOS Data Converter For Communication," Kluwer Academic Publishers, Boston, 2000.
    [6] Kush Gulati and Hae-Seung Lee, "A High-Swing CMOS Telescopic Operational Amplifier," IEEE J. Solid-State Circuits, vol.33, no. 12, pp. 2010-2019, Dec. 1998.
    [7] Zong-Xian Lv, "Design of a Pipelined Analog to Digital Converter for IEEE 802.11a WLAN," Master Thesis, National Chung Hua University, July. 2004.
    [8] Chin-Hsun Chen, " Oversampling with Second-Order Sigma-Delta Modulator," Master Thesis, National United University, June. 2006.
    [9] D. A. Johns and K. Martin, "Analog Integrated Circuit Design," John Wiley & Sons, New York, 1997.
    [10] Hsien-Chun Liu, "Design of a 100MHz 10-Bit Analog to Digital Converter with Pipeline Architecture," Master Thesis, National Chiao Tung University, May. 2003.
    [11] W. Yang, D. Kelly, I. Mehr, M. T. Sayuk and L. Singer, "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input," IEEE J. Solid-State Circuits, vol. 36, pp. 1931-1936, Dec. 2001.
    [12] Phillip E. Allen, and Douglas R. Hollberg, "CMOS Analog Circuit Design," Oxford University Press, Inc. 2002.
    [13] I-Jen Chao, " Design of a 10-bit 50 MHz Pipelined Analog-to-Digital Converter ,"   Master Thesis, Kun Shan University, April. 2007.
    [14] Yu-Yun Huang, "10-bit 50MHx Sampling Rate CMOS Pipelined Analog-to-Digital Converter," Master Thesis, National Yunlin University of Science & Technology, June. 2004.
    [15] Guan-Wei Zheng, "A 1.0-V, 10-Bit CMOS Pipelined Analog-to-Digital Converter," Master Thesis, National Taiwan University, June. 2002.
    [16] Yao-Peng Chen, " Design of High-Speed Analog-to-Digital Converter Based-on Pipelined Architecture ," Master Thesis, Chaoyang University of Technology, Feb. 2005.
    [17] Chih-Peng Hsia, "The design and analysis of a 8-bit 50MS/s pipelined Analog-to-Digital Converter," Master Thesis, National Chung Hua University,Sep. 2005.
    指導教授/口試委員
  • 詹耀福 - 指導教授
  • 徐國政 - 委員
  • 蔡明傑 - 委員
  • 口試日期 2008-10-06 繳交日期 2008-10-14


    基本檢索 | 進階檢索 | 瀏覽檢索 | 檢索歷史