首頁 > 網路資源 > 大同大學數位論文系統

Title page for etd-0117112-215611


URN etd-0117112-215611 Statistics This thesis had been viewed 1788 times. Download 0 times.
Author Shun-an Hsieh
Author's Email Address No Public.
Department Electrical Engineering
Year 2011 Semester 1
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 133
Title THE CONTROLLER IP DESIGN OF MULTIPLE DATA ACCESS PORT FOR DDR SDRAM
Keyword
  • DDR SDRAM
  • Multiple Data Access Port
  • Bus Arbiter
  • Bus Arbiter
  • Multiple Data Access Port
  • DDR SDRAM
  • Abstract At first we introduce the electrical characteristic of the random access memory, including static random access memory(SRAM)and double data rate dynamic random access memory(DDR SDRAM),and consider to construct a multiple data access port memory controller to DDR SDRAM devices.
    In order to implement the multiple data access port function to a single DDR SDRAM device, we use time division multiplexing technique and use a central arbiter to control the resource using scheduling. We also use a flexible weightighting parameter and priority code for those data access ports toachieve good flexible bandwidth share and priority setting when this controller IP is integrated to other circuit.
    We use Verilog 2001 to write the RTL source code and verify the circuit function by simulation tool Modelsim. Finally, we implement the controller by Altera Cyclone IV Family FPGA and use Altera FPGA design tool Quartus II to generate the compilation Report for this design.
    Advisor Committee
  • Yaw-fu Jan - advisor
  • Kou-cheng Hsu - co-chair
  • Shu-chuan Huang - co-chair
  • Yaw-fu Jan - co-chair
  • Files indicate not accessible
    Date of Defense 2012-01-09 Date of Submission 2012-01-18


    Browse | Search All Available ETDs