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Title page for etd-0127111-171108


URN etd-0127111-171108 Statistics This thesis had been viewed 1297 times. Download 19 times.
Author Wei-chieh Chen
Author's Email Address No Public.
Department Communication Engineering
Year 2010 Semester 1
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 66
Title An All-Digital DLL-Based Clock Generator
Keyword
  • phase synchronization
  • multiphase clock generation
  • clock synthesizer
  • Delay-locked loop (DLL)
  • Delay-locked loop (DLL)
  • clock synthesizer
  • multiphase clock generation
  • phase synchronization
  • Abstract In digital processing ICs, on-chip clock is an important signal for operation. Clock performance is relative to the speed and the performance of data process. Multiphase clocks are effective to speed the clock frequency. And multiphase clocks also have low jitter and low skew performance, because multiphase clock generator employs delay-locked loop as based architecture. This thesis present an all-digital DLL-based clock generator. The all-digital multiphase clock generator inculds a time-to-digital converter and a fixed step scheme of phase lock operation to improve DLL’s lock-in range and lock-in time. The all-digital DLL-based clock generator presented in this thesis generates the nine-phase multiphase clock, and then combines nine-phase clock by the frequency synthesizer to produce the multiplied clock.
    Advisor Committee
  • Jie-Cherng Liu - advisor
  • Ching-Huang Wei - co-chair
  • Shu-Chuan Huang - co-chair
  • Files indicate in-campus access only
    Date of Defense 2011-01-14 Date of Submission 2011-01-31


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