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URN etd-0128105-162538 Statistics This thesis had been viewed 2823 times. Download 1737 times. Author Chung-Chu Chia Author's Email Address email@example.com Department Communication Engineering Year 2004 Semester 1 Degree Master Type of Document Master's Thesis Language English Page Count 100 Title DESIGN OF AN EMBEDDED PROCESSOR FOR ADVANCED ENCRYPTION STANDARD Keyword Processor Embedded AES AES Embedded Processor Abstract AES will be the leading algorithm for symmetric encryption and decryption system in the coming thirty years. The speed to accomplish AES algorithm is quite fast when using a parallel architecture. But it costs much more hardware resources and its function is not flexible. If we use a microprocessor to accomplish AES algorithm, it will save more hardware resources and the processor can also accomplish another tasks beside encryption and decryption. In this way, it will become more flexible in application. But its speed still can not be compared with the chip which is designed only for AES. Many thesises try to improve the shortage in speed by some improvements in assembly language programming. This thesis proposes a new architecture of microprocessor designed in embedded soft core which will upgrades the speed to accomplish AES algorithm in an efficient way with shortest code length.
The ALU in a general microprocessor doesn’t have any functions related to AES, so it costs much more code length to accomplish AES encryption and decryption algorithm. This will directly downgrade the efficiency in processing AES algorithm with a longer code length which occupies program memory so much. In this thesis, we designed a 8-bit RISC embedded processor named AESMPU which includes AES functions in its ALU such as modular multiplication, byte substitution and inverse byte substitution. Thus, AESMPU can not only perform general ALU functions but also accomplish AES functions in a machine cycle. This will efficiently upgrade the processing speed in executing AES encryption and decryption when using an embedded processor.
Advisor Committee Shuenn-Shyang Wang - advisor
Ching-Hwa Cheng - co-chair
Teng-Pin Lin - co-chair
Files Date of Defense 2005-01-05 Date of Submission 2005-01-28