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URN etd-0208110-191813 Statistics This thesis had been viewed 2658 times. Download 1188 times. Author CHIN-MIN SHIH Author's Email Address No Public. Department Electrical Engineering Year 2009 Semester 1 Degree Master Type of Document Master's Thesis Language English Page Count 57 Title A 1-V, 10BIT, 10MSAMPLE/S SWITCHED-OPAMP PIPELINED ADC USING OPAMP-SHARING TECHNIQUE Keyword SWITCHED OPAMP PIPELINED ADC ADC POAMP-SHARING POAMP-SHARING ADC PIPELINED ADC SWITCHED OPAMP Abstract In this thesis, a 10-bit 10-MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed and verified by Hspice simulation with TSMC 0.18-µm 1P6M CMOS process models. In order to operation at 1V, the switched-opamp technique is employed in the pipelined ADC. In order to saving the power consumption and chip area, the analog-to-digital converter merges two output stages using an opamp-sharing technique.
The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 51.66 dB with sampling frequency of 10 MHz at input frequency of 530 kHz. Power consumption of this ADC is 18mW with 1V power supply.
Advisor Committee Shu-Chuan Huang - advisor
Files Date of Defense 2010-01-28 Date of Submission 2010-02-08