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Title page for etd-0208110-195635


URN etd-0208110-195635 Statistics This thesis had been viewed 2232 times. Download 1094 times.
Author Pei-Hsin Chiu
Author's Email Address No Public.
Department Electrical Engineering
Year 2009 Semester 1
Degree Master Type of Document Master's Thesis
Language English Page Count 51
Title A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES
Keyword
  • pipelined ADC
  • switched-opamp
  • opamp-sharing
  • loading-free
  • loading-free
  • opamp-sharing
  • switched-opamp
  • pipelined ADC
  • Abstract In this thesis, a 10-bit 10MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed using TSMC 0.18-μm 1P6M CMOS process models. For realizing the pipelined ADC with 1V, an innovative circuit for multiplying digital-to-analog converter (MDAC) is accomplished with the switched-opamp technique without any multiplied voltage circuit or low-threshold process. Furthermore, this thesis proposes a novel pipelined stage by combining the opamp-sharing and loading-free techniques to reduce the capacitive loading and to improve the speed in low-voltage switch circuit. As a result, the proposed pipelined ADC can operate under low power supply and reduce the total power consumption.
    The ADC has been simulated by HSPICE. The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 52.92 dB with sampling frequency of 10MHz at input frequency of 0.55MHz. Power consumption of this ADC is 17.4mW with 1V power supply.
    Advisor Committee
  • Shu-Chuan Huang - advisor
  • Files indicate accessible at a year
    Date of Defense 2010-01-28 Date of Submission 2010-02-08


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