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Title page for etd-0209106-231505


URN etd-0209106-231505 Statistics This thesis had been viewed 1999 times. Download 14 times.
Author Chien-Wei Chen
Author's Email Address No Public.
Department Electrical Engineering
Year 2005 Semester 1
Degree Master Type of Document Master's Thesis
Language English Page Count 71
Title DESIGN AND FPGA IMPLEMENTATION OF A VIDEO SCALAR
Keyword
  • Video scalar
  • scale
  • interpolation.
  • interpolate
  • image scale
  • image scalar
  • image interpolation
  • image interpolation
  • image scalar
  • image scale
  • interpolate
  • interpolation.
  • scale
  • Video scalar
  • Abstract Recently, due to the wide diffusion of multimedia applications and wide area screens (e.g., Widescreen TFT LCD TV), the problem of video format conversion has significantly increased its importance. Video scaling is important in conversion between different formats such as NTSC, PAL, HDTV and between the VGA resolution to the various sizes included in MPEG coding. The architecture suitable for FPGA/ASIC implementation of a video scalar is presented in this paper. Conventional implementation of the filter may result in huge memory and computational requirement. The scheme proposed here results in enormous savings of memory normally required, without compromising on the video quality. In the present work, VGA compatible video sequence is scaled up to WXGA format. The FPGA implementation of the proposed video-scaling algorithm is capable of processing high-resolution, color pictures of sizes up to 1280x768 pixels at the real time video rate of 60 frames/second. The design has been realized by RTL compliant VHDL coding, and fits into a single Xilinx FPGA, and display to TFT-LCD plane that resolution is 1280x768 pixels.
    Advisor Committee
  • Ming-Chien Tsai - advisor
  • Guan-Chyun Hsieh - co-chair
  • Teng-Pin Lin - co-chair
  • Files indicate in-campus access at one year and off-campus not accessible
    Date of Defense 2006-01-20 Date of Submission 2006-02-09


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