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The defense date of the thesis is 2015-02-24
The current date is 2019-05-23
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URN etd-0224115-120005 Statistics This thesis had been viewed 974 times. Download 1 times. Author Kun-Feng Hung Author's Email Address No Public. Department Electrical Engineering Year 2014 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 54 Title A LOW-VOLTAGE LDO REGULATOR WITH TEMPERATURE COMPENSATION WITHIN THE REGULATOR LOOP Keyword error amplifier Low dropout regulator line voltage compensation circuit line voltage compensation circuit Low dropout regulator error amplifier Abstract Low dropout (LDO) linear regulators are widely used in various electronic products, especially in the portable electronic products as an important driver. This research focuses on the design of a low-dropout linear regulator, where the positive temperature coefficient of a PTAT (Proportional To Absolute Temperature) voltage source and the negative temperature coefficient of a CTAT (Complementary To Absolute Temperature) current source cancel each other to solve the temperature drift problems in the traditional LDO regulator. Using line voltage compensation and feedback network achieves stability in the whole load range and provides a stable reference voltage while reducing application costs and ensuring system reliability.
The low dropout linear regulator design is based on TSMC 0.35um CMOS process. The input voltage is 1.8V, the maximum output voltage is 1.5881V, and the maximum output current is 100mA. The whole chip has been designed, simulated, laid out and verified using the EDA software, such as Hspice, Laker, Cadence and Calibre. The validation results indicate when load current is 100mA, the dropout voltage is 211.9mV, and other performance indicators meet the design requirements.
Advisor Committee Prof.Shu-Chuan Huang - advisor
Files Date of Defense 2015-01-23 Date of Submission 2015-02-24