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Title page for etd-0224115-153411


URN etd-0224115-153411 Statistics This thesis had been viewed 1139 times. Download 0 times.
Author Hsiang-Yu Hsieh
Author's Email Address No Public.
Department Electrical Engineering
Year 2014 Semester 1
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 72
Title The Design and Implementation of a Digital Interleaved SEPIC Power Factor Corrector
Keyword
  • PFC
  • Interleaved
  • SEPIC
  • SEPIC
  • Interleaved
  • PFC
  • Abstract This thesis proposes a digital interleaved SEPIC power factor corrector based on microcontroller. First, the SEPIC topology is adopted as the main circuit to possess buck and boost function. Moreover, the microcontroller incorporated with interleaved switching to drive two parallel SEPIC to implement digital interleaved SEPIC power factor correction. In this thesis, we not only introduce the principle of SEPIC, analyze the operation mode of the proposed interleaved SEPIC, but also complete describe the design considerations of the system parameters. In addition, we also introduce how to design the peripheries of microcontroller, and details the program flow of the power factor correction. Finally, a 300W digital interleaved SEPIC power factor corrector is implemented to verify its feasibility by some experimental results.
    Advisor Committee
  • Chang-Hua Lin - advisor
  • Bin-Kwie Chen - co-chair
  • Chien-Ming Wang - co-chair
  • Files indicate in-campus access at 2 years and off-campus not accessible
    Date of Defense 2015-01-30 Date of Submission 2015-02-25


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