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Title page for etd-0308106-133204


URN etd-0308106-133204 Statistics This thesis had been viewed 3359 times. Download 3826 times.
Author Ruei-Hung Chien
Author's Email Address cri.andy@tatung.com
Department Electrical Engineering
Year 2005 Semester 1
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 110
Title A 16/18/20/24-BIT INPUT FORMAT 3rd/5th-ORDER SIGMA-DELTA AUDIO DAC
Keyword
  • Sigma
  • Delta
  • DAC
  • DAC
  • Delta
  • Sigma
  • Abstract Oversampling and sigma-delta modulation techniques have advantages in low bandwidth and high resolution, and have already been used to implement the digital to analog converter (DAC) in the audio system extensively. In this thesis, a sigma-delta DAC suitable for digital audio system has been designed. This circuit provides multiple data input formats (16/18/20/24-bit), multiple input sample rates (44.1kHz/ 88.2kHz/48kHz/96kHz/192kHz) and two different oversampling ratios (128/256). In addition, the order of the modulator can be chosen to be either 3 or 5.
    The system is composed of 3 stages of upsampling digital interpolation filters and a 3rd/5th-order sigma-delta modulator (SDM). The first and second stages of the interpolators are designed as half-band low pass filters, and the third stage is designed as a sinc2 filter. The sigma-delta modulator is based on the Cascade of Integrators Feedback form (CIFB) architecture, and the 3rd- and 5th-order SDMs are designed such that they can share some parts to reduce hardware resources.
    First, MATLAB is used to get the result of system-level simulation and to obtain parameters suitable for hardware implementation. VHDL is used to describe the circuit, and Xilinx ISE6.3 is used for synthesis. The simulation is performed using ModelSim6.0 with a testbench to verify the circuit function and performance, and then the code is downloaded to Xilinx FPGA Virtex-Ⅱand Spartan3 to test the system and to verify the theoretical prediction. Finally, two experimental results are given. For the one with 24bit, 128x oversampling 3rd-order SDM, the signal to noise ratio (SNR) is 92.7dB @ -6dBFS. The other with 24bit, 128x oversampling 5th-order SDM has an SNR of 123.5dB @ -6dBFS.
    Advisor Committee
  • Shu-Chuan Huang - advisor
  • none - co-chair
  • none - co-chair
  • Files indicate in-campus access immediately and off-campus access at one year
    Date of Defense 2005-01-20 Date of Submission 2006-03-08


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