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Title page for etd-0329104-075802


URN etd-0329104-075802 Statistics This thesis had been viewed 2196 times. Download 1531 times.
Author Tzung-Rei Yang
Author's Email Address elixir@amigo.cse.ttu.edu.tw
Department Computer Science and Enginerring
Year 2003 Semester 1
Degree Master Type of Document Master's Thesis
Language English Page Count 71
Title Dynamic Fetch Engine Design for Simultaneous Multithreaded Processors
Keyword
  • Simultaneous Multithreading
  • fetch engine
  • fetch engine
  • Simultaneous Multithreading
  • Abstract Simultaneous Multithreading is a processor design that attempts to combine both the hardware features of superscalar and multithreaded processors, and gain performance by sharing the processor resources dynamically to exploit thread-level parallelism along with instruction-level parallelism. While the fetch unit has been identified as one of the major bottlenecks of this architecture, several fetch schemes were proposed by prior works to enhance the fetching efficiency.
    Among these schemes, ICOUNT, proposed by Tullsen et al. in which priority is assigned to a thread according to the number of instructions it has in the decode unit, register renaming unit and instruction queues were considered to be a great scheme not only the performance it achieved but also in the efficiency of implementation. The ICOUNT scheme works mainly because it favors the thread which fast moving through the pipeline, thus use the resource effectively.
    We think it is better let the thread which tends to have more long latency instructions get the priority at adequate time since long latency instructions are very likely on program’s critical path. We proposed a dynamic fetch scheme which gives the long latency bound thread higher priority while the RUU or LSQ is under low usage. Our motivation is to gain further performance by not only use the resource effectively but also by the urgency of the instructions. The proposed scheme aggressively attacks the LSQ and RUU usage which does further utilize the shared processor resources and achieve overall performance improvements. Experiments show that our scheme achieves 17% speedup in maximum compared to the ICOUNT scheme. Further more, it is easy to implement.
    Advisor Committee
  • Jong-Jiann Shieh - advisor
  • Liang-Teh Lee - co-chair
  • Po-Jen Chuang - co-chair
  • Files indicate access worldwide
    Date of Defense 2004-01-14 Date of Submission 2004-03-29


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