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URN etd-0422105-152949 Statistics This thesis had been viewed 2503 times. Download 1105 times. Author Hung-Chi Wu Author's Email Address No Public. Department Computer Science and Enginerring Year 2004 Semester 1 Degree Master Type of Document Master's Thesis Language English Page Count 136 Title Design and Implementation of Hardware Objects Based on Asynchronous System Technology Keyword soc design IP reuse Hardware Objects Asynchronous circuits design Asynchronous circuits design Hardware Objects IP reuse soc design Abstract This thesis proposes a novel approach to implement reusable hardware objects based on asynchronous system technology. Four hardware object design schemes are proposed and the performance evaluation toward these schemes is carried out by using ALTERA Quarus II. Stack and RSA decryption/encryption IPs are implemented to demonstrate the concepts.
Our goal is to implement reusable hardware objects with adequate performance, less EMI and low power consumption based on asynchronous system technology.
Advisor Committee Fu-Chiung Cheng - advisor
Chang-Jiu Chen - co-chair
Jong-Jiann Shieh - co-chair
Files Date of Defense 2005-01-28 Date of Submission 2005-04-22