Announcement for Downloading full text filePlease respect the Copyright Act.
All digital full text dissertation and theses from this website are authorized the copyright owners. These copyrighted full-text dissertation and theses can be only used for academic, research and non-commercial purposes. Users of this website can search, read, and print for personal usage. In respect of the Copyright Act of the Republic of China, please do not reproduce, distribute, change, or edit the content of these dissertations and theses without any permission. Please do not create any work based upon a pre-existing work by reproduction, Adaptation, Distribution or other means.
URN etd-0512105-103455 Statistics This thesis had been viewed 2607 times. Download 2438 times. Author Huai-Zhe Yang Author's Email Address firstname.lastname@example.org Department Communication Engineering Year 2004 Semester 1 Degree Master Type of Document Master's Thesis Language English Page Count 199 Title DESIGN AND IMPLEMENTATION OF GSM/WCDMA MULTI-MODE DIGITAL IF DOWNCONVERTER Keyword WCDMA software radio interpolation/Decimation GSM digital IF downconverter VHDL VHDL digital IF downconverter GSM interpolation/Decimation software radio WCDMA Abstract Software radios have been widely studied as a solution to support multiple air interface standards in future wireless communications. In this paper, we present an efficient IF processing architecture for a dual-mode GSM/W-CDMA terminal based on the concept of the software radio.
In this thesis, we design an efficient IF processing architecture that can support multi-mode application. The high resolution NCO is implemented in the method of LUT, and allows carrier channels to be selected from a wide frequency band. The high efficient CIC filter provides a wide-range interpolation/decimation rate. The compensating FIR Decimation Filter is used to fix the passband droop error caused by the CIC Filter. The programmable FIR filter aims to reject the out band of signal. Furthermore, this thesis also uses Matlab to decide the interpolation/decimation factor and to simulate the whole system for the purpose of meeting the GSM/WCDMA specification. Finally, we adopt hardware description language ‘VHDL’ for RTL design, and use Xilinx ISE development software to accomplish logic synthesis, circuit place, and route and use Mentor Modelsim SE to accomplish timing verification to complete the multi-mode digital IF downconverter.
Advisor Committee Jie-Cherng Liu - advisor
Chau-Yun Hsu - co-chair
Ching-Huang Wei - co-chair
Files Date of Defense 2005-03-21 Date of Submission 2005-05-12