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Title page for etd-0622106-155205


URN etd-0622106-155205 Statistics This thesis had been viewed 3873 times. Download 1579 times.
Author Der-Fu Tao
Author's Email Address tftao@ntist.edu.tw
Department Computer Science and Enginerring
Year 2005 Semester 2
Degree Ph.D. Type of Document Doctoral Dissertation
Language English Page Count 121
Title PIPORS: A PARALLEL INPUT PARALLEL OUTPUT REGISTER SWITCHING SYSTEM
Keyword
  • Statistical Time Division Multiplexing
  • Shift Register Switch Array
  • Shared Memory Module
  • Parallel Input Parallel Output Register Switchin
  • Central Shared Memory Switching System
  • Central Shared Memory Switching System
  • Parallel Input Parallel Output Register Switchin
  • Shared Memory Module
  • Shift Register Switch Array
  • Statistical Time Division Multiplexing
  • Abstract    In order to make data switch speed fast enough for supporting the current communication systems or networks, a high speed switching system with low data loss and low transmission delay is required.
       Many researchers make use of Statistical Time Division Multiplexing (STDM) technique in the Central Shared Memory Switching System (CSMS) in order to achieve a higher throughput. In the CSMS, the input and output ports share a piece of common memory, where the input data and output data can arrive and possibly be transmitted at the same time respectively. But, the CSMS use multiplexer and demultiplexer at input and output ports respectively for transmitting data. In each time slot the multiplexer and demultiplexer have to process the input data and output data for the input and output ports respectively. Thus, the speed of data transmitted is limited by the number of input and output ports as well as the internal operation speed of the switching system. If the internal operation speed is fixed in switching system, the more input and output ports are included, the lower data transmission speed is observed.
       Furthermore, if the traffic load should be heavy in one of the input ports, the total shared memory will be occupied by this input port. This fact keeps other input ports from transmitting data and results in possible data loss. Therefore, it can not avoid data contention effectively. Furthermore, the control section needs a great deal of memory to store data address, the memory utilization ratio of storing data will be low. This designing philosophy is really not an appropriate way as subjecting to the demand trend for higher speed switching system in the future.
       To overcome the drawbacks of the switching system mentioned above, a new architecture of a Parallel Input Parallel Output Register Switching System (PIPORS) is proposed in this dissertation. The PIPORS is based on the interconnection of the n small distributed/parallel Shared Memory Modules (SMMs) and an n?n Shift Register Switch Array (SRSA), and it is connected in a ring topology. The operations can be performed on n input/output ports simultaneously. By adopting the distributed data storage and data can parallel input/parallel output in the n?n PIPORS simultaneously. Therefore, the switching system contention will effectively be reduced and the internal execution speed must not be n times faster than the speed of input/output port. The performance of PIPORS will be effectively promoted.
       Nowadays, there are many communication system or network applications in which the required size of the switching system is larger than the proposed n?n PIPORS. Therefore, one of the important requirements for designing a switching system is its growability. The architecture should permit modular growth of its size from a small number of ports to a very large switching system. It is also desired that this growth does not result in performance degradation significantly and can meet the requirement of reliability at each stage of the expansion.
       In this dissertation, there are three types of expansion method to be proposed: (1) input/output port size expansion method, (2) memory expansion method, and (3) combined input/output port size and memory expansion method.
    Finally, performance evaluation of a switching system depends on various parameters: total memory required, throughput, data loss probability, and average data delay. Among these, data loss probability is one of the most important factors, and depends strongly on network traffic and buffering method.
       In our simulation, the SMPL (SiMulation Program Language) is adopted to simulate the four different switching systems, Link-list based CSMS, Hybrid CSMS, CAM based CSMS, and PIPORS. According to the results from different simulations as conducted, PIPORS has the merits of the best throughput, the least data loss probability and the shortest average data delay. Therefore, PIPORS is believed to be the most efficient among these switching systems.
    Advisor Committee
  • Liang-Teh Lee - advisor
  • Ge-Ming Chiu - co-chair
  • Hsuan-Shih Lee - co-chair
  • Jeng-Yih Juang - co-chair
  • Tsang-Long Pao - co-chair
  • Yo-Ping Huang - co-chair
  • Files indicate access worldwide
    Date of Defense 2006-06-16 Date of Submission 2006-06-22


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