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Title page for etd-0714106-100604


URN etd-0714106-100604 Statistics This thesis had been viewed 2689 times. Download 20 times.
Author Yu-Chen Shen
Author's Email Address No Public.
Department Electrical Engineering
Year 2005 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 68
Title A 12-BIT 50-MS/S BUILT-IN ANALOG SELF-CALIBRATED PIPELINE ADC
Keyword
  • pipeline ADC
  • Analog self-calibration circuit
  • Analog self-calibration circuit
  • pipeline ADC
  • Abstract This thesis describes a design of a low-power, 12-bit, 50Msample/s, and 3.3-V supply pipeline analog-to-digital converter (ADC). In order to achieve the requirements of digital imaging, where differential nonlinearity (DNL) and integral nonlinearity (INL) are both important, we propose a built-in analog self-calibrated circuit of the ADC in this thesis. Compared with the ADC with the typical digital error correction architecture, our circuit does not need a large and complex digital circuit, but they are replaced by the self-calibration capacitor array and linear-range protection architecture. The entire circuit will be fabricated in a 0.35-um 2P4M CMOS process, the estimated chip area is 2.3×2.2mm2, and the power dissipation is 148mW. Final test results will be reported later.
    Advisor Committee
  • none - advisor
  • none - co-chair
  • none - co-chair
  • Files indicate in-campus access only
    Date of Defense 2006-06-13 Date of Submission 2006-07-14


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