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Title page for etd-0720105-092754


URN etd-0720105-092754 Statistics This thesis had been viewed 1525 times. Download 10 times.
Author Yi-Ko Hsiao
Author's Email Address No Public.
Department Communication Engineering
Year 2004 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 66
Title MEMORY ARCHITECTURE FOR 3GPP TURBO CODE
Keyword
  • Turbo code
  • interleaver
  • 3GPP
  • 3GPP
  • interleaver
  • Turbo code
  • Abstract A great interest has been gained in recent years by a new error-correcting code technique, known as “turbo coding,” which has been proven to offer performance closer to the Shannon’s limit than traditional concatenated codes. Turbo coding offers excellent capabilities of error correction and thus has been getting popular in the wireless applications. However, the implementation of turbo coding requires high computing power and large memory size. In this thesis, we present the design and implementation of 3GPP turbo code. We use the sliding window technique and memory architecture to reduce the complexity and implement turbo decoder on Xilinx Virtex II Pro xc2VP50. The clock frequency of our decoder system can achieve 50MHz. When SNR is 1.5dB, our decoder system BER is close to 10-5.
    Advisor Committee
  • Teng-Pin Lin - advisor
  • Jung-Hui Chiu - co-chair
  • Shuenn-Shyang Wang - co-chair
  • Files indicate in-campus access only
    Date of Defense 2005-07-07 Date of Submission 2005-07-20


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