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The defense date of the thesis is 2013-08-01
The current date is 2019-05-23
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URN etd-0801113-144703 Statistics This thesis had been viewed 1281 times. Download 4 times. Author Chih-Wei Shen Author's Email Address No Public. Department Electrical Engineering Year 2012 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 82 Title A TUNABLE SC DOUBLE-SAMPLING 3-BIT 4TH-ORDER BANDPASS NOISE-COUPLING DELTA-SIGMA MODULATOR WITH DYNAMIC ELEMENT MATCHING TECHNIQUE Keyword delta-sigma modulator noise coupling dynamic element matching dynamic element matching noise coupling delta-sigma modulator Abstract In this thesis, a double-sampling three-bit fourth-order bandpass noise-coupling delta-sigma modulator with dynamic element matching (DEM) is proposed. The design is based on a tunable switched-capacitor (SC) resonator, which can be adjusted to obtain the optimum notch frequencies according to the different bandwidth in different application. Besides, the resonator only requires one opamp in one stage, and therefore the overall power consumption is lower than conventional architecture. The double-sampling technique provides a good method of increasing the sampling frequency and relaxes the performance requirement of the opamp. The active adder with noise coupling technique could avoid any signal attenuation due to parasitic effect, and kick-back noise from the quantizer, and increase the order of the noise transfer function by two without extra circuits. In additional, a dynamic element matching with data-directed scrambler structure is implemented to reduce the harmonic tones caused by the mismatch errors of the capacitors in the internal DAC.
The design is carried out as follows: First, MATLAB and SIMULINK are used to ensure the stability and performance of the structure. Then, the transistor level simulation is done by HSPICE in TSMC 0.18um CMOS 1P6M process. The final implementation of the modulator works at 1.5V supply, 80MHz clock frequency and the center frequency of the input signal is 20MHz. The simulated SNDR is 46.51dB with -4.2dBFS for 5MHz bandwidth and the power consumption is 38.1mW.
Advisor Committee Shu-Chuan Huang - advisor
Chih-Ju Hung - co-chair
Jie-Cherng Liu - co-chair
Files Date of Defense 2013-07-15 Date of Submission 2013-08-01