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The defense date of the thesis is 2004-08-03
The current date is 2018-07-23
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URN etd-0803104-153446 Statistics This thesis had been viewed 2083 times. Download 23 times. Author Chia-Chih Chang Author's Email Address No Public. Department Electrical Engineering Year 2003 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 67 Title A 1.5-V 5-GHz FREQUENCY SYNTHESIZER Keyword PLL FREQUENCY SYNTHESIZER FREQUENCY SYNTHESIZER PLL Abstract A 1.5-V 5-GHz phase-locked loop (PLL) based frequency synthesizer is design in a TSMC 0.18-um CMOS 1P6M technology. We apply the integrated-N architecture to design the frequency synthesizer. The synthesizer consists of a PLL that controls a LC tank voltage-controlled oscillator (VCO) tuned at 5-GHz. The power consumption of the synthesizer is reduced by using a novel divide-by-two circuit as the first frequency divider in the PLL feedback loop.
The synthesizer consumes 22.5 mW of power of which 8.1 mW is consumed by the VCO and the divide-by-two circuit combined. The phase noise is -110 dBc/Hz at 1 MHz offset. This PLL intended for wireless LAN (WLAN) applications can synthesize frequencies between 4.1 and 5.4 GHz.
Advisor Committee Teng-Pin Lin - advisor
Jie-Cherng Liu - co-chair
Wu-shiung Feng - co-chair
Files Date of Defense 2004-07-16 Date of Submission 2004-08-03