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The defense date of the thesis is 2004-08-03
The current date is 2019-04-24
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URN etd-0803104-175521 Statistics This thesis had been viewed 2439 times. Download 18 times. Author Yi-Tai Chang Author's Email Address email@example.com Department Communication Engineering Year 2003 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 79 Title A FULLY INTEGRATED 5.8-GHZ INTEGER-N FREQUENCY SYNTHESIZER Keyword WLAN PLL frequency synthesizer frequency synthesizer PLL WLAN Abstract In this thesis, a 5.8-GHz Integer-N frequency synthesizer is analyzed, designed and implemented in TSMC 0.18um 1P6M CMOS process. The synthesizer, which is designed for use in the upper band of U-NII receiver, consists of a low power, high efficient voltage-controlled oscillator (VCO), and an injection-locked frequency divider (ILFD). The power consumption of the synthesizer is reduced by using an ILFD as the first frequency divider in the PLL feedback loop.
The frequency synthesizer can work in 5.650~5.876GHz that can synthesize 4 channels with every channel space is 20MHz. The total power consumption of the synthesizer is 34.02mW from a single 1.8V supply. It is only 8.37mW that the power is consumed by the VCO and the ILFD combined. The phase noise is -112dBc/Hz at 1 MHz offset. The synthesizer has a bandwidth of 500KHz for a 10MHz reference and the locking time is about 26us, which is suitable for the IEEE 802.11a WLAN applications.
Advisor Committee Teng-Pin Lin - advisor
Jie-Cherng Liu - co-chair
none - co-chair
Files Date of Defense 2004-07-16 Date of Submission 2004-08-03