下載電子全文宣告This thesis is authorized to indicate in-campus access only
You can not download at the moment.
Your IP address is 220.127.116.11
The defense date of the thesis is 2004-08-03
The current date is 2017-09-19
This thesis will be accessible at off-campus not accessible
URN etd-0803104-180500 Statistics This thesis had been viewed 1908 times. Download 9 times. Author Yu-Chi Kao Author's Email Address No Public. Department Communication Engineering Year 2003 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 85 Title DESIGN AND IMPLEMENTATION OF HIGH-ORDER MULTI-BIT SIGMA-DELTA MODULATOR
BY DIGITAL LEVEL CONTROL
Keyword SIGMA-DELTA MODULATOR SIGMA-DELTA MODULATOR Abstract Because the real world signals are analog and the digital form of analog signals can be processed by using flexible digital-signal-processing (DSP), analog to digital conversion becomes the key component in any electronic system.
Although the sigma-delta modulator was first introduced in 1962, it did not gain importance until recent developments in digital VLSI technologies which provide the practical means to implement the large digital signal processing circuitry. The increasing use of digital techniques in communication and audio application has also contributed to the recent interest in cost effective high precision A/D converters.
Basically enhance the signal noise ratio of the sigma delta modulator may obtain by several ways: First, raises the oversampling rate, second, increase the number of system order, third, by use of the multi-bit quantizer. Although the most effective way is to increase the system order, however there might have the stability problem of the sigle-loop architecture when the number of system order is longer than two.
In this thesis we proposed a design method for a stable high-order and multi-bit single-loop sigma delta ADC which does not require a precision multi-bit DAC in the feedback loop. Within the proposed system, the local digital level (DEL) control is employed to extend the integrator output dynamic range.
Advisor Committee Jie-Cherng Liu - advisor
Teng-Pin Lin - co-chair
Wu-Shiung Feng - co-chair
Files Date of Defense 2004-07-16 Date of Submission 2004-08-03