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URN etd-0805104-181202 Statistics This thesis had been viewed 3128 times. Download 1453 times. Author Po-Lan Chen Author's Email Address email@example.com Department Electrical Engineering Year 2003 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 68 Title Design and Implementation of Highly Efficient VLSI Architecture for the 2-D Discrete Wavelet Transform Keyword VLSI Architecture Non-separable Approach 2-D DWT 2-D DWT Non-separable Approach VLSI Architecture Abstract In this thesis, we present a highly efficient VLSI architecture for the direct two -dimensional wavelets transform (2-D DWT), the proposed architecture is based on the recursive pyramid algorithm and systolic VLSI architecture. Then, the filter coefficients of the proposed architecture that use fixed coefficients of Daubechie’s 4-tap wavelets. We proposed the scalable architecture that performs a complete dyadic decomposition of an image in approximately clock cycles (ccs). Therefore, they are at least four times as fast as the other known architecture. And the hardware efficiency of the proposed architecture is not lower than 100%.
This result has been achieved by means of a carefully balanced pipelining, and it has two “face”. First, proposed architecture can be employed for performing processing four times faster than allowed by other architecture working at the same clock frequency (high-speed utilization). Second, it can be employed even using a four times lower clock frequency but reaching the same performance as other architecture. This second possibility allows of
reducing the power dissipation (low-power utilization).
Last, this architecture is designed and simulated by using VHDL as well as it is verified by Xilinx tools. Then, we use FPGA device of Virtex Ⅱ XC2V1000 -5- BG575 to implementation. The work clock frequency is 270 MHz.
Advisor Committee Yaw-Fu Jan - advisor
none - co-chair
none - co-chair
Files Date of Defense 2004-07-21 Date of Submission 2004-08-05