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The defense date of the thesis is 2010-08-11
The current date is 2019-03-22
URN etd-0805110-161211 Statistics This thesis had been viewed 2040 times. Download 0 times. Author Cheng-Che Hsieh Author's Email Address No Public. Department Electrical Engineering Year 2009 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 62 Title DESIGN AND IMPLEMENTATION OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS Keyword ADPLL Phase-Locked Loop Phase-Locked Loop ADPLL Abstract A phase-locked loop (PLL) is a widely used circuit in modern radio communication systems. Traditionally, a PLL is made as an analog building block. However, integrating an analog PLL in a digital noisy systems-on-a-chip (SoC) environment is challenging. In addition, the analog PLL is sensitive to process parameters. It is too hard to use the same analog PLL design in different process. On the other hand, the ADPLL has no off-chip components. It is made from standard cells found in most digital standard cell libraries. Therefore, the ADPLL has the higher immunity for power supply noise, temperature, and process variation.
In this thesis, the ADPLL consists of a digital phase frequency detector, a digital loop filter, a digital controlled oscillator and frequency divider. This thesis proposed a new architecture of digital controlled oscillator has good performance in terms of fine resolution. The ADPLL are developed by Verilog, and they are simulated by ModelSim 6.0i to justify the feasibility of the proposed ADPLL .
Advisor Committee Yaw-Fu Jan - advisor
Files Date of Defense 2010-07-28 Date of Submission 2010-08-11