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URN etd-0806108-113458 Statistics This thesis had been viewed 2681 times. Download 1196 times. Author Chien-Chang Su Author's Email Address No Public. Department Computer Science and Enginerring Year 2007 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 52 Title Low-power Branch Target Buffer Scheme by using Taken Branch Trace Keyword Branch Target Buffer (BTB) Taken Branch Prediction (TBP) Taken Branch Target Buffer (TBTB) Taken Branch Target Buffer (TBTB) Taken Branch Prediction (TBP) Branch Target Buffer (BTB) Abstract In this thesis, we proposed a new branch prediction scheme called Taken Branch Prediction (TBP) to replace traditional architecture. The major mechanism of TBP is that the traditional Branch Target Buffer (BTB) is replaced by a new table called Taken Branch Target Buffer (TBTB). The traditional BTB is lookuped every fetch cycle, but the TBTB is only lookuped when there is instruction seems likely to be a taken branch. As the instruction is likely to be a normal instruction, the TBP is not active. By dynamically profiling the taken branch trace during program execution, our new scheme will almost achieve the goal of one BTB lookup per taken branch.
We use Wattch and SPEC CPU2000 integer and floating-point benchmarks to evaluate the power and performance of this architecture. The simulation tool is the SimpleScalar which is cycle-accurate with cycle-by-cycle.
The experimental results show that our scheme can reduce the branch prediction energy consumption by 39.86% and 52.54% for integer and floating-point benchmarks respectively with only 0.66% performance loss in average for SPEC CPU2000.
Advisor Committee Jong-Jiann Shieh - advisor
Chia-Ming Chang - co-chair
Rung-Bin Lin - co-chair
Files Date of Defense 2008-06-26 Date of Submission 2008-08-07