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URN etd-0806110-132605 Statistics This thesis had been viewed 2701 times. Download 1470 times. Author Tien-yu Huang Author's Email Address No Public. Department Communication Engineering Year 2009 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 73 Title ALL DIGITAL PHASE-LOCKED LOOP WITH ADAPTIVE SEARCHING ALGORITHM Keyword Adaptive ADPLL ADPLL Adaptive Abstract Due to the disadvantages of the traditional analog phase-locked loop (APLL) over source stability, noise interference and design difficulty, the all digital phase-locked loop (ADPLL) can provide better performance than the traditional PLL. The ADPLL is programmable and portable over design that it can efficiently reduce the difficulties in other design process.
This thesis implements an ADPLL with a searching algorithm in its control unit that can perform in high frequency resolutions, and the algorithm provides fast tracking search step to further reduce the lock in time. The ADPLL is simulated with the MATLAB Simulink, and the simulation result shows that when the DCO operating in 0.8GHz-1.4GHz, the lock in time of the reference clock for 134MHz is 1.5μs; when the DCO operating in 1.2GHz-4.35GHz, the lock in time of the reference clock for 300MHz is 0.9μs.
Advisor Committee Jie-cherng Liu - advisor
Hsen-hsin Chou - co-chair
Shu-chuan Huang - co-chair
Files Date of Defense 2010-07-30 Date of Submission 2010-08-06