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The defense date of the thesis is 2007-08-07
The current date is 2019-06-19
URN etd-0807107-180030 Statistics This thesis had been viewed 2218 times. Download 5 times. Author Chia-Hsin Chung Author's Email Address No Public. Department Communication Engineering Year 2006 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 36 Title TWO-LAYER VARIABLE SLOT LENGTH REFLECTARRAY Keyword slot length reflectarray reflectarray slot length Abstract In this thesis, a microstrip patch loaded with a slot is used as an element to realize a 12GHz passive reflectarray on a two-layer substrate. Phase of reflection is adjusted by tuning the length of each slot.
Experimental results showed that the maximum gain is 24.39dB at 11.8GHz. It has a 1.5-dB gain bandwidth of 5.9%. The aperture efficiency is 31.4% and the cross-polarization level is bellow around 25dB
Advisor Committee The-Nan Chang - advisor
Jean-Fu Kiang - co-chair
Jie-Cherng Liu - co-chair
Files Date of Defense 2007-07-20 Date of Submission 2007-08-07