首頁 > 網路資源 > 大同大學數位論文系統

Title page for etd-0808113-153315


URN etd-0808113-153315 Statistics This thesis had been viewed 1373 times. Download 0 times.
Author Han-Jie Ma
Author's Email Address No Public.
Department Electrical Engineering
Year 2012 Semester 2
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 65
Title DESIGN AND IMPLEMENTATION OF A PHASE-LOCKED LOOP CIRCUIT
Keyword
  • PLL
  • PLL
  • Abstract This thesis presents a phase-locked loop (PLL) with operation at 2.5GHz. The phase-locked loop consists of a phase frequency detector , charge pump, loop filter,voltage controlled oscillator and frequency divider. The voltage controlled oscillator is a ring oscillator without inductance, and can reduce the chip area. The total power consumption of the phase-locked loop is 24.35mW and the locking time is about 4μ sec.
    The PLL is implemented by TSMC 0.18-μm single-poly/six metal CMOS process. The ADS simulation results justify the feasibililty of the proposed phase-locked loop .
    Advisor Committee
  • Yaw-Fu Jan - advisor
  • Shuenn-Shyang Wang - co-chair
  • Files indicate not accessible
    Date of Defense 2013-07-29 Date of Submission 2013-08-12


    Browse | Search All Available ETDs