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Title page for etd-0808113-193116


URN etd-0808113-193116 Statistics This thesis had been viewed 1206 times. Download 0 times.
Author Jen-Hsien Huang
Author's Email Address No Public.
Department Electrical Engineering
Year 2012 Semester 2
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 53
Title FPGA DESIGN OF AES ALGORITHM FOR MOBILE DEVICES
Keyword
  • aes
  • cbc
  • fpga
  • mobile
  • mobile
  • fpga
  • cbc
  • aes
  • Abstract In this thesis, we present a chip of the encryption and decryption with 128, 192, and 256 bits of keys based on the AES (Advanced Encryption Standard) algorithm. It can connect to a smart phone, a tablet PC, a computer through communication to complete the work of the encryption and decryption and it deals with the data in CBC (Cipher Block Chaining) mode of 128 bits. The AES can be used in a variety of Electronic Funds Transfer applications.
    I want reducing hardware resources to gain a compact and efficient implementation circuit for mobile devices.
    To realize the chip of this design, the CBC mode encryption and decryption chip use Verilog, Altera tool, Modelsim to design and simulate. We use FPGA (Altera Arria II GX, EP2AGX45CU17C6 development environment) to implement it.
    The gate count ALUTs is 3966. The operating clock rate is 150MHz, Data throughput is about 500Mbit/sec.
    Advisor Committee
  • Yaw-Fu Jan - advisor
  • none - co-chair
  • Shuenn-Shyang Wang - co-chair
  • Files indicate in-campus access at 5 years and off-campus access at 10 years
    Date of Defense 2013-07-29 Date of Submission 2013-08-12


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