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Title page for etd-0810111-000137


URN etd-0810111-000137 Statistics This thesis had been viewed 1678 times. Download 0 times.
Author Wen-Jiun Huang
Author's Email Address No Public.
Department Electrical Engineering
Year 2010 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 56
Title DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS
Keyword
  • pll
  • all digital
  • all digital
  • pll
  • Abstract In this thesis, we design an all-digital phase-locked loop (ADPLL) circuit in which resolution in the frequency detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The ADPLL generates output clock frequency with only four reference clock. A ring-delay-line consisting of 32 stages makes it possible for both the frequency detector and DCO to have a common time base, resulting in this unique clock generator. The pulse delay circuit is connected in a ring shape with 32 inverters ( inverters).With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. The generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock for a high-speed response. The frequency synthesizers are developed by Verilog, and they are simulated by Modelsim to justify the feasibility of the proposed frequency synthesizer.
    Advisor Committee
  • Yaw-Fu Jan - advisor
  • none - co-chair
  • none - co-chair
  • Files indicate not accessible
    Date of Defense 2011-07-27 Date of Submission 2011-08-10


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