||The phase- locked loop (PLL) has been widely used in different field such as computer, consumer electronics, and communication , etc. We have to overcome many complicated problems to integrate a analog PLL into the single chip system full of noise. The sensitive process change of analog PLL would result in much noise and other problems. Therefore, we have to redesign the parameters of analog components in different processer and it usually takes a lot of time. In order to solve all the issues, all-digital design is option. Because all-digital circuit means that we use the components of a digital standard cell library to design the circuit only, there is no external unit in the structure of the circuit. Thus, an all-digital PLL has high immunity to temperature change and noise during the process.
In this thesis, the structure of an all-digital PLL contains phase frequency detectors, time to digital converters, control units, digitally controlled ring oscillators and frequency dividers. We use the time to digital converter with a new kind of structure to help get the quantitative phase error. Form the result of circuit simulation, with several different set of reference signal input, the system is converged and locked. The working frequency range for this ADPLL is about 152~574MHz. Finally, we use the Xilinx Spartan3E XC3S1600E-5FG320 FPGA with ModelSim 6.1f and ISE 9.1i to test all the feasibility and functionality of the circuit.