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URN etd-0813115-131417 Statistics This thesis had been viewed 815 times. Download 0 times. Author Yu-sheng Su Author's Email Address No Public. Department Electrical Engineering Year 2014 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 72 Title The Study of Time-to-Digital Converters with Fault Correction Keyword Successive Approximation Register Time-to-Digital Converter redundancy redundancy Time-to-Digital Converter Successive Approximation Register Abstract In this thesis, a time-to-digital converter (TDC) with fault correction is presented. The architecture of the proposed TDC adopts a successive approximation (SAR) algorithm with redundancy for automatic correction. Despite fault digital codes maybe appear in circuits due to process, voltage, and temperature variation, if the target value locates in the range of the redundancy, the phase difference of the last stage will be less than the value of the least significant bit.
The proposed TDC is implemented in TSMC 0.18µm 1P6M CMOS process. The frequency of reference signal and input signal are 25MHz and 10MHz, respectively. When the phase difference between both reference signal and input signal is 9ns, the phase difference of the last stage of the proposed TDC and its resolution are 23ps and 39ps, respectively. The power consumption of the proposed TDC is 3.07mW @ 1.8V and its core area is 0.118mm2.
Advisor Committee Ming-lang Lin - advisor
Shu-chuan Huang - co-chair
Song-Rong Han - co-chair
Files Date of Defense 2015-07-17 Date of Submission 2015-08-13