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The defense date of the thesis is 2004-08-20
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URN etd-0820104-134033 Statistics This thesis had been viewed 2226 times. Download 16 times. Author Bo-Tsang Huang Author's Email Address No Public. Department Electrical Engineering Year 2003 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 66 Title THE DESIGN OF SECOND-ORDER 3-BIT DELTA-SIGMA MODULATOR USING DYNAMIC ELEMENT MATCHING METHOD Keyword DELTA-SIGMA DELTA-SIGMA Abstract The design of a delta-sigma analog-to-digital converter is presented. It uses a 3-bit second-order modulator with dynamic element matching (DEM) to reduce the linearity requirements for the feedback DAC. The DEM algorithm is implemented in such a way to minimize the additional delay within the feedback loop of the modulator.
For an oversampling ratio of 200, the converter achieves a signal-to-noise ratio (SNR) of 97 dB in the signal band. The converter is sampled at 10 MHz and signal bandwidth is 25 kHz. The analog circuit design will be implemented in a TSMC 0.35 CMOS technology, and consumes 20 mW from s 3.3-V power supply. It is shown that the SNR in the signal band for 5% mismatch in DAC is degraded to 40 dB. In addition, the non-linearity of the DAC due to capacitance mismatch generates a large second harmonic distortion. If DEM is employed, the SNR would be improved to 80 dB. The unwanted noise in the spectrum above the Nyquist band can be removed by using a decimator. For a two-stage FIR filters and eight times downsampling, the overall SNR for the entire ADC is 93dB, which is equivalent to 15-bit resolution.
Advisor Committee Shu-Chuan Huang - advisor
Jie-Cherng Liu - co-chair
Wan-Rone Liou - co-chair
Files Date of Defense 2004-07-30 Date of Submission 2004-08-20