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Title page for etd-0820104-134046


URN etd-0820104-134046 Statistics This thesis had been viewed 2491 times. Download 28 times.
Author Chang-Ping Chang
Author's Email Address No Public.
Department Electrical Engineering
Year 2003 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 104
Title THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT
Keyword
  • PLL
  • FREQUENCY SYNTHESIZER
  • FREQUENCY SYNTHESIZER
  • PLL
  • Abstract Based on the phase-locked-loop (PLL) design concepts, this thesis presented the designs of a RF frequency synthesizer with a LC-tank voltage-controlled oscillator and a clock and data recovery (CDR) circuit with a ring oscillator. The implementation of the frequency synthesizer for 802.11a includes the building blocks such as the phase frequency detector, charge pump, loop filter and prescaler. A high-speed prescaler is designed based on injection-locked and Miller frequency dividers. The implementation of the CDR circuit for 2.488GHz optical communications is also presented. The building blocks of CDR that including phase detector, charge pump, loop filter and VCO are discussed and designed. The circuits are simulated with simulink and ADS to verify the system- and transistor- level performances based on TSMC 0.18um CMOS one-poly six-metal (1P6M) technology with a 1.8V supply.
    Advisor Committee
  • Shu-Chuan Huang - advisor
  • none - co-chair
  • none - co-chair
  • Files indicate in-campus access only
    Date of Defense 2004-07-30 Date of Submission 2004-08-20


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