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URN etd-0820113-141931 Statistics This thesis had been viewed 766 times. Download 2 times. Author Yuan-Feng Chen Author's Email Address No Public. Department Computer Science and Enginerring Year 2012 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 101 Title AUTOMATIC SYNTHESIS OF QDI SEQUENTIAL CIRCUITS FROM SYNCHRONOUS SEQUENTIAL SPECIFICATIONS Keyword Synchronous Circuit translate to Asynchronous Ci Synchronous Circuit translate to Asynchronous Ci Abstract Quasi-Delay insensitive (QDI) circuits are the most robust and practical that can be built and are resilient to process, temperature and voltage variations. Although there are many research papers that can translate synchronous designs into asynchronous sequential designs. To the best of our knowledge, there are neither algorithms nor tools that automatically translate a synchronous design or synchronous FSM (finite state machine) into a QDI FSM.
We propose three QDI FSM models (i.e. NCLD FSM、NCLX FSM and ROC FSM) and an algorithm that can automatically synthesizes QDI FSMs from synchronous FSM specifications. An EDA tool written in Java is then developed to translate synchronous design spec such as Verilog and VHDL into these kinds of QDI FSMs. One of the distinguish feature is that the behaviors of our QDI FSM design is the same as those of the corresponding synchronous FSM in terms of functionality. This greatly simplifies the verification complexity and reduces verification cost.
Two set of circuits (i.e. verifiable benchmark circuits and ISCAS-89) are exploited to carry out performance evaluation. The experimental results show that our ROC FSMs use the least hardware cost and NCLX FSMs consume lowest energy in average.
Advisor Committee Fu-Chiung Cheng - advisor
Chun-Yao Wang - co-chair
none - co-chair
Files Date of Defense 2013-07-29 Date of Submission 2013-08-20