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Title page for etd-0821109-142359


URN etd-0821109-142359 Statistics This thesis had been viewed 2448 times. Download 1113 times.
Author Hui-Ya Hsu
Author's Email Address No Public.
Department Electrical Engineering
Year 2008 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 92
Title A DOUBLE-SAMPLING THREE-BIT FOURTH-ORDER BANDPASS DELTA-SIGMA MODULATOR BASED ON TUNABLE RESONATORS
Keyword
  • DEM
  • double-sampling
  • noise coupling
  • bandpass delta-sigma modulator
  • tunable resonator
  • tunable resonator
  • bandpass delta-sigma modulator
  • noise coupling
  • double-sampling
  • DEM
  • Abstract In this thesis, a switched-capacitor (SC) double-sampling three-bit fourth-order bandpass delta-sigma modulator with tunable resonators and active adder opamp based on feed-forward topology is proposed. The feed-forward topology can reduce the distortion in the signal path, and efficiently reduce the circuit complexity and physical area, especially when the loop contains a multi-bit quantizer. The tunable resonator can optimize modulator performance for band of interest by adjusting the resonator frequency with selecting switches, and the resonator just needs one operation amplifier to realize that can reduce the power consumption. Additionally, double-sampled technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier. An active adder opamp is used before the quantizer to avoid any signal attenuation due to parasitics, and any kick-back noise from the quantizer. In addition, we also presented the self-coupling bandpass noise shaping, and sorting algorithm DEM, and they are verified by the system level simulation.
       The design procedure is summarized in the following: First, we can use MATLAB and SIMULINK to verify the stability and estimate the performance. Then, Hspice is used for transistor level simulation. The final implementation of the modulator works at 1.5V supply and clock frequency is 40MHz (effective frequency would be 80MHz), the input center frequency is 20MHz in TSMC 0.18?m CMOS 1P6M process. Simulation results reveal that the peak SNDR is 47.48dB and 62.42dB with -12dBFS input for bandwidth 5MHz (OSR=8) and bandwidth 0.625MHz (OSR=64), respectively, and power consumption is 46mW.
    Advisor Committee
  • Shu-Chuan Huang - advisor
  • none - co-chair
  • none - co-chair
  • Files indicate in-campus access at 2 years and off-campus access at 2 years
    Date of Defense 2009-07-31 Date of Submission 2009-08-21


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