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URN etd-0822108-155654 Statistics This thesis had been viewed 2314 times. Download 1327 times. Author Hsin-Yu Chen Author's Email Address No Public. Department Electrical Engineering Year 2007 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 58 Title A 1-V, 10BIT, 10MSAMPLE/S SWITCHED-OPAMP PIPELINED ADC USING LOADING-FREE AND OPAMP-SHARING TECHNIQUES Keyword loading-free opamp-sharing switched-opamp pipelined ADC pipelined ADC switched-opamp opamp-sharing loading-free Abstract In this thesis, a 10-bit 10-MHz pipelined analog-to-digital converter (ADC) consisted of 1.5-bit/stage has been designed and implemented in TSMC 0.18-µm 1P6M CMOS process. In order to operate at 1 V, the pipelined analog-to-digital converter uses switched-opamp technique. In addition, this thesis proposes a novel pipelined stage by combining the opamp-sharing and loading-free techniques to reduce the power consumption. An opamp with two output stages is employed to merge opamp-sharing and switched-opamp structures. The passive sample-and-hold (S/H) replaces the conventional sample-and-hold circuit to save power. This work only needs five opamps in the pipelined ADC. Therefore, the proposed pipelined ADC can operate under low power supply and reduce the total power consumption. The ADC has been simulated by HSPICE. The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 55.13 dB with sampling frequency of 10 MHz at input frequency of 595 kHz. Power consumption of this ADC is 19mW with 1V power supply. The chip area of this pipelined ADC is 1.38mm×1.38mm without digital error correction. The measurement results will be reported later. Advisor Committee Shu-Chuan Huang - advisor
none - co-chair
none - co-chair
Files Date of Defense 2008-07-29 Date of Submission 2008-08-22