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Title page for etd-0822112-125642


URN etd-0822112-125642 Statistics This thesis had been viewed 1485 times. Download 0 times.
Author Hung-ju Chang
Author's Email Address No Public.
Department Electrical Engineering
Year 2011 Semester 2
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 63
Title DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS
Keyword
  • all digital phase locked loop
  • ADPLL
  • time to digital converter
  • time to digital converter
  • ADPLL
  • all digital phase locked loop
  • Abstract In this thesis, we designed an all digital phase locked loop (ADPLL). Its structures included phase frequency detectors, time to digital converter, loop filter, digital controlled oscillators, buffer and divider. This thesis not only proposed a new modified time to digital converter which can transform all the impulse into a digital string signal but also modified the circuits of buffer which make all the circuits work well and without interfering of signal delay. Finally, we know that the ranges of locking frequency error are -0.68%~1.62%. The output frequency ranges are 152~581MHz. In this thesis, we use Xilinx Spartan3E XC3S1600E-5FG320, MODELSIM PE 10.1a and ISE 10.1 to check new modified time to digital converter, BUF and all other circuits.
    Advisor Committee
  • Yaw-Fu Jan - advisor
  • Files indicate in-campus access at 15 years and off-campus access at 20 years
    Date of Defense 2012-07-30 Date of Submission 2012-08-22


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