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URN etd-0822114-113153 Statistics This thesis had been viewed 1946 times. Download 654 times. Author Chih-Hsiang Huang Author's Email Address No Public. Department Electrical Engineering Year 2013 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 67 Title FULL ON-CHIP LOW-VOLTAGE LDO REGULATOR COMPENSATED WITH CURRENT AMPLIFIERS Keyword Low dropout regulator bandgap reference circuit current amplifier of compensation network current amplifier of compensation network bandgap reference circuit Low dropout regulator Abstract Low dropout linear regulator (LDO) has been widely used in various electronic products, especially in the rapid development of portable electronic products, where long battery life has become the most important thing. This research focuses on the design of a low-dropout linear regulator with low cost, low noise, high efficiency, high PSRR, and stable voltage. The circuit includes a quick start circuit to solve the long start-up time problem that is caused by the parasitic capacitance. Using internal current amplifier compensation network achieves stability in the whole load range and improves load transient response while reducing application costs and ensuring system reliability.
The low dropout linear regulator design is based on TSMC 0.35um CMOS process. The input voltage range is 1.2V ~ 4.5V, output voltage is 1V, and the maximum output current is 100mA. A bandgap reference circuit has been designed to provide a stable reference voltage of 1V. The whole chip has been designed, simulated, laid out and verified using the EDA software, such as Hspice, Laker, Cadence and Calibre. The validation results indicate when load current is 100mA, the dropout voltage is 205.29mV, and other performance indicators meet the design requirements. The entire chip area is about 1058um x 1055um (not including I/O PADs).
Advisor Committee Shu-Chuan Huang - advisor
Files Date of Defense 2014-07-22 Date of Submission 2014-08-25