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Title page for etd-0823105-120511


URN etd-0823105-120511 Statistics This thesis had been viewed 2018 times. Download 11 times.
Author Wen-Bing Shieh
Author's Email Address No Public.
Department Electrical Engineering
Year 2004 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 99
Title PCI INTERFACE SOC PLATFORM DESIGN
Keyword
  • PCI
  • Platform
  • SOC
  • SOC
  • Platform
  • PCI
  • Abstract ABSTRACT
       This thesis proposed a general purpose and basic platform for the SoC investigation in the future which includes three major interconnect bus : the PCI bus, the Wishbone bus and the Microprocessor bus, also consists some other common buffers such as dual port memory, FIFOs and some state machines, and UART port as a LCD interface.
       The PCI Local bus is a high performance 32-bit or 64-bit bus with multiplexed address and data lines, which is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in-cards and processor/memory systems. 
       The WISHBONE System-on-Chip (SoC) interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integration problems. Wishbone is public domain standard.
       The microprocessor is selected with a very popular and common used 8051 micro-controller. It’s a 8-bit microprocessor IP, and integrate with sequencer, instructions set, internal memory, general purpose registers etc.
       Combine the IPs above and some dual port memory, FIFOs and UART, it becomes a general purpose SoC platform and easy to extend with PCI or Wishbone bus which are popular in the current SoC design field.
    Advisor Committee
  • Teng-Pin Lin - advisor
  • Chienhua Chen - co-chair
  • Wu-Shiung Feng - co-chair
  • Files indicate in-campus access only
    Date of Defense 2005-07-28 Date of Submission 2005-08-23


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