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URN etd-0823111-151404 Statistics This thesis had been viewed 3828 times. Download 4001 times. Author Man-Chuen Choi Author's Email Address No Public. Department Electrical Engineering Year 2010 Semester 1 Degree Master Type of Document Master's Thesis Language English Page Count 76 Title LOW-DROPOUT LINEAR REGULATORS WITH Q REDUCTION Keyword LOW DROPOUT LINEAR REGULATORS LOW DROPOUT LINEAR REGULATORS Abstract The popularization and rapid growth of portable electronic products results in that more and more attention has been paid to the high performance and low cost power manage projects. As a competitive kind of power management, the new generation of low dropout linear regulator (LDO) with ultra low noise, high PSRR, micro-power loss and the lowest cost will be holding an important position.
This thesis focuses on the design of a low dropout linear regulator (LDO) IC with improved stability. Not only lead to the reduction of the required PCB space and component cost, but also make the power management more efficient and reasonable. In order to improve efficiency, the PMOS transistor is adopted to achieve the low dropout voltage. The bypass circuit is designed to reduce the output voltage noise and improve power supply rejection, which make the chip adapt to audio devices. Furthermore, its fast start-up circuit is designed to reduce the start-up time. The circuit is added to ensure the stability in whole load range, improve the transient response and greatly reduce the cost of the application.
Based on the principle of LDO and TSMC 0.35um CMOS process, the whole chip and its sub-blocks have been designed and simulated using the EDA software, such as View Draw, Hspice and Laker. The results of simulation indicate that the dropout voltage is just 190.6mV at the condition of output current 150mA, and all of other characteristics meet the specification. The layout area is 1058μm x 947μm without I/O PADs.
Advisor Committee Shu-Chuan Huang - advisor
Files Date of Defense 2011-07-12 Date of Submission 2011-08-23