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Title page for etd-0823113-125642


URN etd-0823113-125642 Statistics This thesis had been viewed 1098 times. Download 0 times.
Author Ya-Chen Hsieh
Author's Email Address No Public.
Department Computer Science and Enginerring
Year 2012 Semester 2
Degree Master Type of Document Master's Thesis
Language zh-TW.Big5 Chinese Page Count 69
Title Use Hybrid Echo Instruction to Reduce Code-size In MIPS
Keyword
  • hybrid ech
  • echo instruction
  • compress code size
  • compress code size
  • echo instruction
  • hybrid ech
  • Abstract Embedded Systems are heavily affected by cost、power and performance. How to design such a system that costs lower without compromising its functionality is always an important topic.
     In this paper, we focus on code size compression for embedded system. We pick the so called 「ECHO algorithm」 to be our compression scheme and make enhancement on it. Such an enhancement is achieved by combining different 「ECHO Instruction configurations」 to make improvement. Although the proposed method isn’t too complex, it does achieve a very good compression ratio under our experiment.
     Besides the algorithm, this paper makes further consideration about how to adapt the proposal to real world application. By leveraging existed MIPS architecture, and exploring the unused instruction patterns, the modified MIPS instruction set should be able to recognize those new added “compressed” instructions. Even the possible hardware implementation is briefly discussed.
     Furthermore, this paper also proposes using “post-compilation” process, which analyze and produce the compressed image after normal compilation flow. This means that the original MIPS tool chain can still be reused without further change.
    Advisor Committee
  • Jong-Jiann Shieh - advisor
  • Chia-Ming Chang - co-chair
  • Shih-Ming Cho - co-chair
  • Files indicate in-campus access at 5 years and off-campus not accessible
    Date of Defense 2013-07-26 Date of Submission 2013-08-26


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