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The defense date of the thesis is 2006-08-24
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URN etd-0824106-133721 Statistics This thesis had been viewed 1974 times. Download 15 times. Author Yuan-Hung Hsu Author's Email Address No Public. Department Communication Engineering Year 2005 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 61 Title ?DESIGN AND IMPLEMENTATION OF A VITERBI DECODER WITH IMPROVED RADIX-4 BUTTERFLY MODULE Keyword radix-4 butterfly Viterbi decoder Viterbi decoder butterfly radix-4 Abstract In this paper we presents a new radix-4 butterfly design for Viterbi decoders. The branch symmetry of the proposed radix-4 butterfly is exploited to design a reduced radix-4 butterfly module to simplify the implementation of the soft-decision Viterbi decoder. By exploiting the branch symmetry, only a half of branch metrics need to be computed, while other metrics can be derived from the computed branches. Therefore, the branch metric computation of the radix-4 butterfly can be reduced by a factor of 2.Then we use the proposed reduced module to build a Viterbi decoder and described in VHDL code. Finally synthesis and simulation has be done by using ISE 6.1i(Xilinx synthesis tool) and ModelSim XE III 6.0a(simulation tool).
Experimental results indicate that the proposed radix-4 butterfly design can reduce the number of FPGA slices of the radix-4 butterfly module by 19% over the conventional design; moreover, the Viterbi decoder with proposed radix-4 butterfly modules can reduce the number of slices about 11%.
Advisor Committee Chau-yun Hsu - advisor
Teng-pin Lin - co-chair
Wei-mei Chen - co-chair
Files Date of Defense 2006-06-12 Date of Submission 2006-08-24