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Title page for etd-0825109-154221


URN etd-0825109-154221 Statistics This thesis had been viewed 2362 times. Download 961 times.
Author Reui-Hung Hung
Author's Email Address No Public.
Department Communication Engineering
Year 2008 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 100
Title DESIGN AND IMPLEMENTATION OF VARIABLE-LENGTH FAST FOURIER TRANSFORM PROCESSORS FOR MIMO OFDM SYSTEMS
Keyword
  • MIMO
  • OFDM
  • FFT
  • FFT
  • OFDM
  • MIMO
  • Abstract In this thesis, we propose two pipeline designs of multiple-input multiple-output (MIMO) variable-length fast Fourier transform (FFT) processors for WLAN and WiMAX applications. One is 128/64-point FFT processor with 1-4 data sequences for IEEE 802.11n WLAN, and the other is 256/128/64-point FFT processor with 1-4 data sequences for IEEE 802.11n WLAN and IEEE 802.16 WiMAX. By investigating several FFT algorithms and comparing the computational complexity , we choose the mix-radix FFT algorithms in our designs. Moreover, we adopt the multiple-path delay commutator (MDC) architecture to efficiently realize our processors. It is due to the fact that the multiple-path delay commutator FFT architectures require fewer delay elements and the mixed-radix FFT algorithms need fewer complex multiplications. It is shown that the proposed processors can achieve high throughput for 1-4 data sequences. Using UMC 0.18um process, their area are 1.5162mm^2 and 2.5122mm^2,respectively. These two processors can correctly perform 4 data sequences FFT up to 50 MHz with 213.9 mW and 511.3 mW, respectively.
    Advisor Committee
  • Shuenn-Shyang Wang - advisor
  • Lan-Da Van - co-chair
  • Yaw-Fu Jan - co-chair
  • Files indicate accessible at a year
    Date of Defense 2009-07-23 Date of Submission 2009-08-25


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