Announcement for Downloading full text filePlease respect the Copyright Act.
All digital full text dissertation and theses from this website are authorized the copyright owners. These copyrighted full-text dissertation and theses can be only used for academic, research and non-commercial purposes. Users of this website can search, read, and print for personal usage. In respect of the Copyright Act of the Republic of China, please do not reproduce, distribute, change, or edit the content of these dissertations and theses without any permission. Please do not create any work based upon a pre-existing work by reproduction, Adaptation, Distribution or other means.
URN etd-0826104-173556 Statistics This thesis had been viewed 2719 times. Download 1735 times. Author Li-an Chiang Author's Email Address No Public. Department Computer Science and Enginerring Year 2003 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 50 Title Design and Implementation of Hardware/Software Codesign for SoC CAD Tool Keyword Software Profiling Partitioning Hardware/Software Codesign Hardware Information Extraction Hardware Information Extraction Hardware/Software Codesign Partitioning Software Profiling Abstract Embedded system designers are constantly looking for new tools and techniques to help satisfy the exploding demand for consumer information appliances and specialized industrial products. One critical barrier to the timely release of embedded system products is integrating the design of the hardware and software systems. In addition to its critical role in the development of embedded systems, co-design is a key design methodology for Systems-on-a-Chip.
CAD tools that can easily help to proceed codesign is necessary. In this paper, we propose a new hardware/software codesign methodology targets reconfigurable architectures (FPGA), and develop a codesign system for our SOCAD tool. The SOCAD contains a translator that can translate Java code into VHDL code based on self-timed cell library.
The partitioning algorithm in the codesign system uses the Saving Time Cost Effective strategy to select the beneficial and critical methods. The number of logic elements to each method is the constraint. There will output VHDL codes for hardware part and Java code for Software part in the end.
Advisor Committee Fu-chiung Cheng - advisor
Jong-jiann Shieh - co-chair
none - co-chair
Files Date of Defense 2004-07-22 Date of Submission 2004-08-26