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URN etd-0826104-174426 Statistics This thesis had been viewed 2908 times. Download 1129 times. Author Chi-Huam Shieh Author's Email Address No Public. Department Computer Science and Enginerring Year 2003 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 50 Title Automatic Detection and Generation of Self-Timed Pipeline Keyword VHDL Translation System-on-a-chipIntellectual Properties Self-Timed System Pipelining Pipeline Activity Diagram Activity Diagram Pipeline Pipelining Self-Timed System System-on-a-chipIntellectual Properties Translation VHDL Abstract Behavior synthesis is becoming the major design methodology for System-on-a-chip (SOC) design with IP (Intellectual Property) reuse to solve the productivity gap problem. Pipeline mechanism can be applied to the behavior models to improve performance. This thesis presents a new methodology to automatically detect and generate self-timed pipeline mechanism from high-level language descriptions.
Self-timed pipeline modules (i.e. StagePipeline, DecoderPipelineModule and DoubleRegx32) are designed. Then pipeline detection and generation algorithm automatically inserts self-timed pipeline modules to behavior models to improve performance.
Simple Java processor is designed and used to test our methodology. The experimental results show that a non-pipeline Java processor can be automatically partition into three stages and the pipelined Java processor is 1.99 times faster than the non-pipeline version with only 2.8% more hardware logic.
Advisor Committee Fu-Chiung Cheng - advisor
none - co-chair
none - co-chair
Files Date of Defense 2004-07-22 Date of Submission 2004-08-26