首頁 > 網路資源 > 大同大學數位論文系統

Title page for etd-0827108-171809


URN etd-0827108-171809 Statistics This thesis had been viewed 1899 times. Download 18 times.
Author Lin Chao Ho
Author's Email Address No Public.
Department Electrical Engineering
Year 2007 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 94
Title CMOS LNA DESIGN FOR ULTRA-WIDEBAND WIRELESS RECEIVERS
Keyword
  • CMOS UWB LNA
  • CMOS UWB LNA
  • Abstract This thesis describes the design of an UWB (3.1GHz – 10.6GHz) low-noise amplifier employing a common-gate stage for wideband input matching in TSMC 0.18-μm 1P6M CMOS process. To achieve the desired gain and output matching, a common-source and source follower stages are used for the second and third stages, respectively. The proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single chip CMOS UWB receiver. According to the requirements of the MB-OFDM, the RF front-end circuit of the UWB receiver is demonstrated by the performances of the input return loss, isolation, power gain, output return loss, noise figure, group delay, and 1dB compression with the ADS simulation. The proposed UWB LAN achieves 13.7 ± 1.5dB power gain with good input and output match (S11 and S22 < -13dB) over 7500MHz bandwidth (from 3.1 GHz to 10.6GHz), and average noise figure is 3.5dB. With 1.8-V power supply, the total power consumption is about 19mW. A gain control mechanism is also introduced by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets. The Layout of the UWB LNA is about .
    Advisor Committee
  • Shu Chuan Huang - advisor
  • Files indicate in-campus access only
    Date of Defense 2008-07-25 Date of Submission 2008-09-01


    Browse | Search All Available ETDs