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URN etd-0830111-151912 Statistics This thesis had been viewed 1864 times. Download 1417 times. Author Jau-Shian Huang Author's Email Address No Public. Department Computer Science and Enginerring Year 2010 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 59 Title Synthesizing SystemC Programs into Synchronous Circuits Keyword SystemC High level synthesis Finite State Mach Finite State Mach High level synthesis SystemC Abstract The design complexity to build SOC (System On a Chip) products is increasing and becoming more complex with the advance in technology. One promising way to solve the design complexity or productivity gap is high-level synthesis.
SystemC is the IEEE standard to support high-level synthesis. This thesis proposes an efficient method to translate SystemC programs into synchronous sequential circuits based on a graph notation. In particular, the SystemC programs are translate into a set of sub-graphs. Each sub-graph corresponds to a state in finite state machine. The sub-graphs are then translated into VHDL codes which are verified in Altera Quartus tool.
The experimental results show that the circuits synthesized by our translation methodology have the low worst case delay and have larger number of states.
Advisor Committee Fu-Chiung Cheng - advisor
Chang-Jiu Chen - co-chair
Jong-Jiann Shieh - co-chair
Files Date of Defense 2011-07-28 Date of Submission 2011-08-31