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The defense date of the thesis is 2005-08-31
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URN etd-0831105-164415 Statistics This thesis had been viewed 1967 times. Download 16 times. Author Kun-Chiung Chen Author's Email Address No Public. Department Electrical Engineering Year 2004 Semester 2 Degree Master Type of Document Master's Thesis Language English Page Count 63 Title A DOUBLE-SAMPLED FOURTH-ORDER BANDPASS DELTA-SIGMA MODULATOR BASED ON FEEDFORWARD TOPOLOGY FOR LOW-POWER DESIGN Keyword delta-sigma modulator delta-sigma modulator Abstract ABSTRACT
The design of an 80MHz fourth-order bandpass delta-sigma modulator with a double-delay, single-opamp resonator plus double sampling technique is proposed for GSM standard. The double-delay resonator uses only one opamp to reduce power dissipation, while double-sampling technique relaxes the performance requirement for the opamp. The circuit is based on the feedforward topology to reduce the distortion in the signal path. The circuit will be implemented in TSMC 0.35μm double-poly, four-metal CMOS process. Both behavioral-level and transistor-level simulation results are presented, and the circuit is expected to achieve 80dB peak SNR, and less than 40mW power consumption at 3.3V supply. According to HSPICE simulation, a peak SNR of 65dB is achieved for 200kHz signal bandwidth with sampling frequency of 40MHz (equivalent to 80MHz). The resonator is built using a high performance gain-boosted folded-cascade opamp. The opamp achieves 85dB of DC gain, 361 MHz GBW at 3.3V supply.
Advisor Committee Shu-Chuan Huang - advisor
Jie-Cheng Liou - co-chair
Wan-Rung Liou - co-chair
Files Date of Defense 2005-06-27 Date of Submission 2005-08-31