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URN etd-0831111-095007 Statistics This thesis had been viewed 1864 times. Download 1043 times. Author Heng-Wei Chang Author's Email Address No Public. Department Computer Science and Enginerring Year 2010 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Page Count 46 Title Design and Implementation of Decimal Floating Point Hardware Accelerators on Nios II Platform Keyword Nios II Hardware Accelerator Decimal Floating Point Decimal Floating Point Hardware Accelerator Nios II Abstract Floating Point Units are a vital part of digital systems. Recently, there is increasing interest in decimal floating-point arithmetic research due to many commercial and financial-based applications which require Decimal Floating Point arithmetic. The problem of using binary floating-point arithmetic in commercial and financial calculations is that most decimal floating-point numbers cannot be represented exactly in binary floating-point formats, and thus unacceptable errors may occur in the course of the computations. Therefore, these applications usually use software library instead, such as Java’s BigDecimal and C#’s Decimal, suffering from performance penalty.
Hardware decimal arithmetic units now are becoming an integral part of recently commercialized general purpose processors. This thesis designs and implements both software algorithms and hardware acceleration of Decimal Floating Point Arithmetic for Nios II platform. The experimental results show that C2H hardware accelerator, Custom Peripheral and Custom Instruction are 37 to 47, 96 to 447 and 976 to 4542 times faster than software functions, respectively.
Advisor Committee Fu-Chiung Cheng - advisor
Chang-Jiu Chen - co-chair
Jong-Jiann Shieh - co-chair
Files Date of Defense 2011-07-28 Date of Submission 2011-08-31