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Title page for etd-0902105-152419


URN etd-0902105-152419 Statistics This thesis had been viewed 1966 times. Download 19 times.
Author Shin-Yi Song
Author's Email Address No Public.
Department Communication Engineering
Year 2005 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 67
Title Investigation and Design of a Variable Length FFT Processor for OFDM Communication Systems
Keyword
  • variable length FFT processor
  • pipelined architecture
  • OFDM
  • OFDM
  • pipelined architecture
  • variable length FFT processor
  • Abstract This paper proposes a variable length FFT processor for Orthogonal Frequency Division Multiplex(OFDM) communication systems. We use radix-2/4/8 algorithm in pipelined architecture, which can effectively minimize the number of complex multiplications. Due to radix-2/4/8 algorithm has regularity. So, it is easy to be implemented in VLSI, especially in a pipelined architecture. Besides, in order to reduce the required chip area and power consumption, we need fixed-point arithmetic, and twiddle factors are stored one-eighth period sine and cosine ROM .
    Based on this architecture, a variable- length FFT is designed for use in the 802.11a DAB, DVB-T, ADSL and VDSL applications. It can deal with 64 to 8192 points FFT. Finally, The chip we used is Xilinx XC2V 1000 FG456 which achieve radix-2/4/8 FFT architecture, we also use the logic analyzer to verify our simulation result.
    Advisor Committee
  • Deng-Bin Lin - advisor
  • Wu-Shiung Feng - co-chair
  • Yau-Fu Jan - co-chair
  • Files indicate in-campus access at one year and off-campus not accessible
    Date of Defense 2005-07-28 Date of Submission 2005-09-02


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