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Title page for etd-0902105-161507


URN etd-0902105-161507 Statistics This thesis had been viewed 3030 times. Download 1500 times.
Author Yu-Tang Chang
Author's Email Address No Public.
Department Electrical Engineering
Year 2004 Semester 2
Degree Master Type of Document Master's Thesis
Language English Page Count 43
Title An FPGA design and implementation of the AES in OCB mode of operation
Keyword
  • AES OCB FPGA
  • AES OCB FPGA
  • Abstract In this thesis, we use FPGA(X2CV-1000, 0.18μm CMOS process, 3.3V power supply) to design AES_OCB mode operation. We use Verilog, Xilinx ISE 6.1 and ModelSim to design simulate and implement. The number of CLB slices is 3552.The operating clock rate is 61.31MHz. Data throughput is about 603Mbit/sec.
    Advisor Committee
  • Y.F. Jan - advisor
  • none - co-chair
  • S.S Wang - co-chair
  • Files indicate access worldwide
    Date of Defense 2005-07-27 Date of Submission 2005-09-02


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